1. Field of the Invention
The present invention generally relates to power management in data processing systems, and more particularly to a method of controlling power usage of a memory structure such as dynamic, random-access memory (DRAM).
2. Description of the Related Art
Power usage has become a dominant concern in the development of data processing systems. Excess power usage is not only costly and inefficient, but also leads to heat management problems. These problems are particularly pronounced in computer systems having large amounts of memory, such as server systems. Servers typically use dynamic random-access memory (DRAM) which is preferable over other memory structures such as static random-access memory (SRAM) because DRAM is more dense. However, DRAM is much more power intensive. SRAM uses a flip-flop memory cell but DRAM uses a capacitor-based memory cell which, due to current leakage, must be regularly refreshed. DRAM can consume up to 45% of a system's overall power.
Power optimization techniques for memory subsystems can generally be classified into three categories: hardware-based methods (implemented within a memory controller), software-directed techniques (compiler or operating system), and hybrid approaches. A basic hardware mechanism for reducing power is to put memory devices into a low-power mode when they are idle. Unfortunately, the overuse of this mechanism can limit performance as there are associated entrance and exit latencies for a particular low power mode. More intelligent memory controllers have been devised which use schedulers in conjunction with power-down commands. Their goal is to try to match predicted idle time with a low-power mode that has the appropriate latency to resume activity. Variations of this approach basically monitor usage of memory sections (ranks) and move to a different power level if the usage exceeds a threshold level. Since threshold values are system- and application-dependent, the algorithms are difficult to tune. These hardware-based approaches for power savings assume in-order scheduling of the memory commands.
Compiler-directed approaches aim to group memory accesses to the same memory sections to increase the size of idle periods. This goal is achieved by loop transformations, data layout optimizations, instruction scheduling, or a combination of these methods. In cacheless single-processor systems, compile-time techniques can help the memory controller make better predictions for idle periods of memory sections, but in systems with multi-level caches or with shared memory controllers the role of the compiler for power savings is limited.
Operating system (OS) support for power savings may be implemented as a first order design criteria, for example, by shutting down unused system components to save energy. By controlling the set of physical devices that are in active use, the actual power consumption for their access can be controlled by putting inactive devices into low-power mode. This approach has been used to change the size of allocated memory for processes by tracking page miss rate versus memory size curve. Other OS-based approaches rely on improving the placement of data in physical memory. Better page allocation policies can save energy; for example, by allocating new pages to memory that is already in use (or using page migration), the number of active memory devices can be kept to a minimum. One OS performance optimization is the activation of memory used by a newly scheduled process during a context switch, which largely hides the latency of exiting low-power mode. Another OS-based approach reshapes memory traffic at the page granularity. However, with the use of large page sizes, OS-based techniques which require data migration may degrade performance considerably. Any approach that minimizes the number of active memory devices also reduces the available memory bandwidth which can adversely affect performance. Accesses previously performed in parallel to different memory devices may need to be performed serially to the same memory device.
Hybrid approaches propose a cooperative software-hardware mechanism that tracks process-specific idle periods to exploit low-power modes for ranks of DRAM devices. Processor and DRAM power can be jointly managed by attempting to maximize system performance for a given total power budget, which is particularly useful when either the CPU or DRAM is significantly less utilized than the other. These approaches are not transparent to software and so can entail significant programming difficulties.
Memory controllers have also been devised which attempt to optimize memory performance without relying on low-power modes. These controllers use intelligent schedulers to reorder memory commands. FIG. 1 depicts an example of such a memory controller 10 which uses a plurality of arbiters 12 to reorder commands based on counts of read commands and write commands. Incoming memory commands (read or write) are stored in reorder queues 14, and a selector 16 keeps track of read command count (Rcnt), write command count (Wcnt), and a count of the number of cycles elapsed since the last arbiter selection (Ccnt). Firmware 18 stores setup information and control instructions to dynamically select the most appropriate read/write arbiter from among arbiters 12 based on the current read/write pattern (ratio). The selected arbiter then determines the next command to be sent to the memory array. Arbiter selection is repeated periodically, i.e., when Ccnt reaches a predetermined count. In a system where bank conflicts cause long delays, some commands in reorder queues may be blocked until conflicts related to those commands are resolved.
While memory schedulers that reorder commands can significantly improve performance, they are unfortunately at odds with memory schedulers that use power-down modes. For optimal performance, a reorder scheduler typically selects commands that avoid hardware conflicts, essentially spreading the commands across many physical memory devices. However, to reduce power consumption, a power-aware scheduler would cluster commands to a subset of the physical devices, allowing one or more of them to be put into low-power mode. It would, therefore, be desirable to devise an improved memory controller which could optimize performance while still taking advantage of low-power modes. It would be further advantageous if the controller could be used to minimize performance degradation for a given power budget.